A capacitance Cgs may be generated between a gate electrode and a source electrode of a thin film transistor (TFT), and a potential at a pixel may be pulled down due to a potential at the gate electrode. During the manufacture of the TFT, an overlapping offset may easily occur between a gate layer and a source/drain (SD) layer, and it is impossible for a conventional TFT design to ensure a constant Cgs. In addition, the larger the Cgs is, the larger the potential (ΔVp) at the pixel to be pulled down is, and the larger a grayscale difference formed by an identical signal voltage in the case of polarity conversion is. At this time, such a phenomenon as flickering may occur for an image. Hence, an additional scheme for compensating for the Cgs needs to be provided. The Cgs compensation design has been widely applied in the pixel design for a thin film transistor liquid crystal display (TFT-LCD), and it is mainly used to ensure a stable Cgs and prevent the occurrence of such display defects as flickering.
Generally, it is able to compensate for ΔVp merely by adjusting a potential at a common electrode (COM) to be a median value of the signal voltage. However, in the case that a Cgs difference occurs for an identical batch of products, it is difficult to compensate for the potential at the common electrode, and thereby a display effect of the products may be adversely affected. Hence, it is impossible for this Cgs compensation scheme to achieve an ideal effect.
Hence, there is an urgent need to provide a scheme, so as to prevent the occurrence of such display defects as flickering for the TFT-LCD, due to the unstable capacitance Cgs generated between the gate electrode and the source electrode of a TFT.